The present invention relates to a semiconductor design technology, and more particularly, to a high-speed semiconductor memory apparatus. More particularly, the present invention relates to a high-speed semiconductor memory apparatus capable of autonomously performing a clock alignment training therein.
A semiconductor memory apparatus stores data in a system including a plurality of semiconductor memory apparatuses. When a data processing apparatus, for example, a memory control unit (MCU), requests data, a semiconductor memory apparatus outputs data corresponding to an address inputted from the data requesting apparatus, or stores data provided from the data requesting apparatus in a location corresponding to the address.
To this end, a high-speed memory apparatus is designed to input/output two data between a rising edge and a falling edge, and input/output two data between the falling edge and the following rising edge in a system clock applied from the outside. That is, a high-speed memory apparatus is designed to input/output four data in a cycle of a system clock.
However, since the system clock has only two states—logic high or logic low, a data clock having a frequency two times faster than a system clock is required to input/output four data in a cycle. That is, a dedicated clock for data input/output is required.
Accordingly, a high-speed semiconductor memory apparatus uses a system clock as a reference clock when transmitting/receiving an address and a command, and uses a data clock as a reference clock when inputting/outputting data, thereby controlling the data clock to have a frequency two times higher than that of the system clock.
That is, four data may be inputted/outputted in a cycle of a system clock by allowing two cycles of the data clock to be repeated during a cycle of the system clock, and allowing data input/output to be generated in a rising edge and a falling edge of the data clock.
Unlike a conventional DDR synchronization memory apparatus using a single system clock as a reference in order to perform a read or write operation, a high-speed semiconductor memory apparatus uses two clocks having different frequencies to transmit/receive data for the read or write operation.
However, if phases of the system clock and the data clock are not aligned, timings for delivering the operation command and the address and references for the data are not aligned. This means that the high-speed semiconductor memory apparatus may not operate normally.
Accordingly, an interface training operation between a semiconductor memory apparatus and a data processing apparatus must be performed at the initial stage for normal operation of a high-speed semiconductor memory apparatus.
The interface training operation is for training the high-speed semiconductor memory apparatus so as to operate at a timing point when an interface for delivering commands, addresses, and data is optimized before normal operation is performed between the semiconductor apparatus and the data processing apparatus.
The interface training is divided into an address training, a clock alignment training (WCK2CK training), a read training, and a write training. An operation of aligning a data clock and a system clock is performed in the clock alignment training.
FIG. 1 is a block diagram illustrating a typical circuit for performing a clock alignment training.
To explain the basic principles of the clock alignment training, a high-speed semiconductor memory apparatus, as described above, receives an address signal and a command signal from an external memory controller based on a system clock HCK, and outputs data stored in the semiconductor memory apparatus to the external memory controller based on a data clock WCK.
If there is a phase difference between the system clock HCK and the data clock WCK, the data stored in the semiconductor memory apparatus arrives at the external memory controller at timings faster or slower than intended timings by a duration corresponding to the phase difference.
Accordingly, a clock alignment training is performed to reduce a phase difference between the system clock HCK and the data clock WCK by detecting the phase difference between the system clock HCK and the data clock WCK, and transmitting the detection result to the external memory controller.
The typical circuit for performing the clock alignment training described in FIG. 1 is a circuit for detecting a system clock HCK and a data clock WCK from an external memory controller, and performing an operation for transmitting the detection result to the external memory controller.
Referring to FIG. 1, the circuit includes a clock input unit 100, a clock division unit 120, a phase detection unit 140, and a signal transmission unit 160. The clock input unit 100 receives a system clock HCK for synchronizing input timing points of an address signal and a command signal, and a data clock WCK (having a higher frequency than the system clock HCK) for synchronizing an input timing point of a data signal received from an external memory controller. The clock division unit 120 divides a frequency of the data clock WCK to generate a data division clock DIV_WCK so that the data division clock DIV_WCK may have the same frequency as the system clock HCK. The phase detection unit 140 detects a phase difference between the system clock HCK and the data division clock DIV_WCK, and generates a detection signal DET_SIG corresponding to the detection result. The signal transmission unit 160 transmits the detection signal DET_SIG as a training information signal TRAINING_INFO_SIG to the external memory controller.
FIG. 2 is a timing diagram illustrating operation waves of a typical circuit for performing a clock alignment training in FIG. 1.
Referring to FIG. 2, while a frequency of a data clock WCK inputted from an external memory controller to a typical circuit for performing a clock alignment training is higher than that of a system clock HCK, a frequency conversion unit 120 converts the frequency of the data clock WCK to be identical to the frequency of the system clock HCK. Accordingly, the frequency of the data clock DIV_WCK outputted from the frequency conversion unit 120 is identical to the frequency of the system clock HCK.
Before a clock alignment training operation is performed ({circle around (1)}), clock edges are not synchronized with each other. That is, the phases of the data clocks WCK and DIV_WCK and the system clock HCK are not synchronized with each other before the clock alignment training operation.
After the clock alignment training operation ({circle around (2)}, {circle around (3)}, {circle around (4)}, {circle around (5)}, and {circle around (6)}), the phases of the data clocks WCK and DIV_WCK are changed to synchronize with the phase of the system clock HCK while the phase of the system clock HCK is not changed.
In this case, the phases of the data clocks WCK and DIV_WCK are changed in accordance with a logic level of a training information signal DET_SIG (TRAINING_INFO_SIG) transmitted to the external memory controller by the signal transmission unit 160. That is, because the logic level of the training information signal DET_SIG (TRAINING_INFO_SIG) is continuously a logic low level, the external memory controller changes the phases of the data clocks WCK and DIV_WCK bit by bit to apply to the circuit for performing the clock alignment training.
When the phases of the data clocks WCK and DIV_WCK are synchronized with the phase of the system clock HCK {circle around (6)}, the logic level of the training information signal DET_SIG (TRAINING_INFO_SIG) is changed from the logic low level to the logic high level. The phases of the data clocks WCK and DIV_WCK are not changed in the section {circle around (7)} continually maintained at the logic high level. That is, since the logic level of the training information signal DET_SIG (TRAINING_INFO_SIG) is in a logic high state, the external memory controller fixes the phases of the data clocks WCK and DIV_WCK to apply to the circuit for performing the clock alignment training.
In conclusion, the circuit for performing the clock alignment training allows the phase detection unit 140 to continuously compare phases of the data dock WCK and the system clock HCK until the phases of the data clock WCK and the system clock HCK inputted from the external memory controller are synchronized, and transmits the comparison result, i.e. the training information signal DET_SIG (TRAINING_INFO_SIG) to the external memory controller.
However, the clock alignment training operation is disadvantageous in that much time is required until the phase of the data clock WCK is changed and inputted after a training information signal DET_SIG (TRAINING_INFO_SIG) is generated in the semiconductor memory apparatus and transmitted to the external memory controller.
That is, the phase of the data clock WCK is changed and inputted when a certain time elapses after a training information signal DET_SIG (TRAINING_INFO_SIG) is generated in the semiconductor memory apparatus and transmitted to the external memory controller.
Thus, the clock alignment training operation takes time to complete.
Furthermore, in a system sharing a memory such as a dual back memory, an accurate clock alignment training operation may be difficult to obtain when considering a delay skew of a transmission path from a memory controller to each memory.